A typical FinFET is three dimensional complementary metal oxide semiconductor (CMOS) structure disposed upon a planar substrate. A conducting FET channel between source and drain regions is surrounded on three or more sides by one or more gate electrodes giving the FinFET more volume than a planar gate FET in the same planar area. The surrounding gate electrode(s) control current flow through the conducting channel and, ideally, very little current is allowed to pass through the channel when the FinFET is in the off state. The FinFET has been used to fabricate CMOS transistors at least since the technology evolved to the 22 nm regime.
While the FinFET source/drain (S/D) regions can be doped by ion implanting a suitable dopant species, typically the FinFET employs an epitaxially grown S/D in order to reduce resistance. Such epitaxially grown S/Ds may be referred to as (in situ doped) raised S/Ds (RSDs).
A problem that can arise during the epitaxial growth of RSDs relates to a formation of undesirable semiconductor nodules that have a potential to create an electrical short circuit.